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ML3440
Micropower Synchronous Buck-Boost DC/DC Converter Description
The ML3440 is a high efficiency, fixed frequency, Buck-Boost DC/DC converter that operates from input voltages above, below or equal to the output voltage. The topology incorporated in the IC provides a continuous transfer function through all operating modes, making the product ideal for single lithium-ion, multicell alkaline or NiMH applications where the output voltage is within the battery voltage range. The device includes two 0.19 N-channel MOSFET switches and two 0.22 P-channel switches. Switching frequencies up to 2MHz are programmed with an external resistor and the oscillator can be synchronized to an external clock. Quiescent current is only 25uA in Burst Mode operation, maximizing battery life in portable applications. Burst Mode operation is user controlled and can be enabled by driving the MODE/SYNC pin high. If the MODE/SYNC pin has either a clock or is driven low, then fixed frequency switching is enabled. ML3440 include a 1uA shutdown, soft-start control, thermal shutdown and current limit. The ML3440 is available in the 10-pin thermally enhance MSOP package.
Features
Single Inductor Fixed Frequency Operation with Battery voltages Above, Below or Equal to the Output. Synchronous Rectification: Up to 96% Efficiency 25uA Quiescent current in Burst Mode Operation Up to 600mA continuous Output Current No schottky Diodes Required (VOUT <4.3V) VOUT Disconnected from VIN During Shutdown 2.5V to 5.5V Input and Output Range Programmable Oscillator Frequency from 300KHz to 2MHz Synchronizable Oscillator Burst Mode Enable control <1uA Shutdown Current Small Thermally Enhanced 10-Pin MSOP Package
Applications
Palmtop Computers Handheld Instruments MP3 Players Digital Cameras
Ordering Information
Item Package MSOP-10 Shipping 1000/ Tape&Reel ML3440SRG
Typical Application
Efficiency vs VIN
ML3440
1/13
Rev. B, Sep 2005
Marking Rules
Description Symbol 3 4 B
Pin Configuration
1 2 3 4
Product : ML3440 Item VFB = 1.22 V
Block Diagram
2/13
Rev. B, Sep 2005
Pin Function
RT (Pin 1): Timing Resistors to program the Oscillator Frequency. The programming frequency range is 300KHz to 2MHz. 6 1010 Fosc = Hz RT MODE/SYNC (Pin2): MODE/SYNC = External CLK : Synchronization of the internal oscillator. A clock frequency of twice the desired switching frequency and with a pulse width between 100ns and 2us is applied. The oscillator free running frequency is set slower than the desired synchronized switching frequency to guarantee sync. The oscillator RT component value required is given by: 8 1010 Fsw = desired synchronized switching frequency. RT = GND (Pin 5): Signal and Power Ground for the IC.
VOUT (Pin 6): Output of the Synchronous Rectifier. A filter
capacitor is placed from VOUT to GND.
VIN (Pin 7): Input Supply Pin. Internal Vcc for the IC. A
ceramic bypass capacitor as close to the VIN pin and GND (Pin 5) is required. SHDN/SS (Pin 8): combined Soft-Start and Shutdown. Grounding this pin shuts down the IC. Tie to >1.5V to enable the IC and >2.5V to ensure the error amp is not clamped from soft-start. An RC from the shutdown command signal to this pin will provide a soft-start function by limiting the rise time of the Vc pin. FB (Pin 9): Feedback Pin. Connect resistor divider tap here. The output voltage can be adjusted from 2.5V to 5.5V. The feedback reference voltage is typically 1.22V. Vc (Pin 10): Error Amp Output. A frequency compensation network is connected from this pin to the FB pin to compensate the loop.
where fSW
SW1 (pin 3): Switch Pin where the Internal Switches A and B are connected. Connect inductor form Sw1 to Sw2. An optional Schottky diode can be connected from Sw1 to ground. Minimize trace length to keep EMI down. SW2 (Pin4): Switch Pin Where the Internal Switches C & D are connected. For applications with output voltages over 4.3V, a Schottky diode is required from SW2 to VOUT to ensure the SW pin does not exhibit excess voltage.
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Rev. B, Sep 2005
Absolute Maximum Ratings (Ta=25 oC, VIN =3.6V, RT=60K, unless otherwise noted)
Parameter VIN, VOUT Voltage SW1, SW2 Voltage Vc, RT, FB Voltage SHDN/SS Voltage MODES/SYNC Voltage Operating temperature Range Storage Temperature Range Lead TEMPERATURE (Soldering, 10sec) Rating -0.3 ~ 6 -0.3 ~ 6 -0.3 ~ 6 -0.3 ~ 6 -0.3 ~ 6 0to 70 -65 to 125 300 Unit V V V V V
Electrical Characteristics (Ta=25 oC, VIN =3.6V, RT=60K, unless otherwise noted)
Parameter Input Start-Up voltage Input Operating Range Output Voltage Adjust Range Feedback voltage Feedback Input current Quiescent Current, Burst Operation. Quiescent current, Shutdown Quiescent Current, Active NMOS Switch Leakage PMOS Switch Leakage NMOS Switch On Resistance PMOS Switch On Resistance Input current Limit Maximum Duty Cycle Minimum Duty Cycle Frequency Accuracy MODE/SYNC Threshold MODE/ SYNC Input Current Error Amp AVOL Error Amp Source Current Error Amp Sink Current SHDN/SS Threshold Condition * * * * Mode VFB=1.22V VC=0V, MODE/SYNC=3V (Note 1) SHDN=0V, Not Including Switch Leakage Vc=0V, MODE/SYNC=0V, Switches B and C Switches A and D Switches B and C Switches A and D Boost (% Switch C on) Buck (% Switch A on) * * * * * 1 5.5 100 0.8 0.4 Min 2.5 2.5 1.196 Typ. 2.4 Max 2.5 5.5 5.5 1.244 50 40 1 1000 5 10 Unit V V V V nA uA uA uA uA uA A % % % MHz V uA dB uA uA V V uA
1.22 1 25 0.1 600 0.1 0.1 0.19 0.22 75
1 0.01 90 15 380 1 2.2 0.01
VMODE/SYNC=5.5V
0 1.2 2 1
When IC is Enabled When EA is at Maximum Boost Duty Cycle SHDN/SS Input Current VSHDN = 5.5V The * denotes specifications that apply over the full operating temperature range Note 1: Current measurements are performed when the outputs are not switching.
*
0.4
1.5 1
4/13
Rev. B, Sep 2005
Operation (1)
The ML3440 provides high efficiency, low noise power for applications such as portable instrumentation. The error amp output voltage on the Vc pin determines the output duty cycle of the switches. Since the Vc pin is a filtered signal, it provides rejection of frequencies from well below the switching frequency. The low RDS(ON), low gate charge synchronous switches provide high frequency pulse width modulation control at high efficiency. Schottky diodes across the synchronous switch D and synchronous switch B are not required, but provide a lower drop during the break-before-make time (typically 15ns). The addition of the Scchottky diodes will improve peak efficiency by typically 1% to 2% at 600KHz. High efficiency is achieved at light loads when Burst Mode operation is entered and when the IC's quiescent current is a low 25uA.
Supply Current Limit
The current limit amplifier will shut PMOS switch A off once the current exceeds 2.7A typical. The current amplifier delay to output is typically 50ns.
Reverse Current Limit
The reverse current limit amplifier monitors the inductor current form the output through switch D. Once a negative inductor current exceeds-400mA typical, the IC will shut down switch D.
Output Switch Control
Figure 1 shows a simplified diagram of how the four internal switches are connected to the inductor, VIN, VOUT and GND. Figure 2 shows the regions of operation for the ML3440 as a function fo the internal control voltage, VCI. The VCI voltage is a level shifted voltage form the output the error amp (Vc pin)(see Figure 5). The output switches are properly phased so the transfer between operation modes is continuous, filtered and transparent to the user. When VIN approaches VOUT the Buck/Boost region is reached where the conduction time of the four switch region is typically 150ns. Referring to Figures 1 and 2, the various regions of operation will now be described.
Low Noise Fixed Frequency Operation Oscillator
The frequency of operation is user programmable and is set through a resistor from the RT pin to ground where f= 6e10 RT Hz
An internally trimmed timing capacitor resides inside the IC, the oscillator can be synchronized with an external clock applied to the MODE/SYNC pin. A clock frequency of twice the desired switching frequency and with a pulse width between 100ns and 2us is applied. The oscillator RT component value required is given by: 8 1010 fsw
RT =
Where fSW = desired synchronized switching frequency. For example to achieve a 1.2MHz synchronized switching frequency the applied clock frequency to the MODE/SYNC pin is set to 2.4MHz and the timing resistor, RT, is set to 66.5k (closest 1% value).
Figure 1 Simplified Diagram of Output Switches
Error Amp
The error amplifier is a voltage mode amplifier, The loop compensation components are configured around the amplifier to provide loop compensation for the converter. The SHDN/SS pin will clamp the error amp output, Vc, to provide a soft-start function.
Figure 2 Switches Control vs Internal Control Voltage, VCl
5/13
Rev. B, Sep 2005
Operation (2)
Low Noise Fixed Frequency Operation Buck Region (VIN > VOUT)
Switch D is always on and switch C is always off during this mode. When the internal control voltage, VCI is above voltage V1, output A begins to switch. During the off time of switch A, synchronous switch B turns on for the remainder of the time. Switches A and B will alternate similar to a typical synchronous buck regulator. As the control voltage increases, the duty cycle of switch A increases until the maximum duty cycle of the converter in Buck mode reaches DMAX_BUCK, given by: DMAX_BUCK =100 - D4SW % where D4SW = duty cycle% of the four switch range D4SW = (150ns f) 100% where f = operating frequency, Hz. Beyond this point the "four switch," or Buck/Boost region is reached.
Burst Mode Operation
Burst Mode Operation is when the IC delivers energy to the output until is regulated and then goes into a sleep mode where the outputs are off and the IC is consuming only 25uA. In this mode the output ripple has a variable frequency component that depends upon load current. During the period where the device is delivering energy to the output, the peak current will be equal to 400mA typical and the inductor current will terminate at zero current for each cycle. In this mode the maximum average output current is given by: 0.1 VIN VOUT + VIN
Iout
(MAX)BURST
A
Buck/Boost or four Switch (VIN - VOUT)
When the internal control voltage, VCI, is above voltage V2, switch pair AD remain on for duty cycle DMAX-BUCK, and the switch pair AC begins to phase in. As switch pair AC phases in, switch pair BD phases out accordingly. When the VCI voltage reaches the edge of the Buck/Boost range, at voltage V3, the AC switch pair completely phase out the BD pair, and the boost phase begins at duty cycle D4SW . The input voltage, VIN, where there four switch region begins is given by: VOUT 1- (150ns f )
Burst Mode operation is user controlled, by driving the MODE/SYNC pin high to enable and low to disable. The peak efficiency during Burst Mode operation is less than the peak efficiency during fixed frequency because the part enters full-time 4-switch mode (when servicing the output) with discontinuous inductor current as illustrated in Figures 3 and 4. During Burst Mode operation, the control loop is nonlinear and cannot utilize the control voltage from the error amp to determine the control mode, therefore full-time 4-switch mode is required to maintain the Buck/Boost function. The efficiency below 1mA becomes dominated primarily by the quiescent current and not the peak efficiency. The equation is given by: (bm) ILOAD 25uA + ILoad
Efficiency Burst
Where (bm) is typically 79% during burst Mode operation for an ESR of the inductor of 50m. For 200m of inductor ESR, the peak efficiency (bm) drops to 75%.
VIN =
V
The point at which the four switch region ends is given by: VIN = VOUT (1-D) = VOUT (1-150ns f )V
Boost Region (VIN < VOUT)
Switch A is always on and switch B is always off during this mode. When the internal control voltage, VCI, is above voltage V3, switch pair CD will alternately switch to provide a boosted output voltage. This operation is typical to a synchronous boost regulator. The maximum duty cycle of the converter is limited to 75% typical and is reached when VCI is above V4.
Figure 3 Inductor Charge Cycle During Burst Mode Operation
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Rev. B, Sep 2005
Operation (3)
Low Noise Fixed Frequency Operation Burst Mode Operation (2) SOFT-START
The soft-start function is combined with shutdown. When the SHDN/SS pin is brought above typically 1V, the IC is enabled but the EA duty cycle is clamped from the Vc pin. A detailed diagram of this function is shown in Figure 5. The components Rss and Css provide a slow ramping voltage on the SHDN/SS pin to provide a soft-start function.
Figure 4 Inductor Discharge Cycle During Burst Mode Operation
Burst Mode Operation to Fixed Frequency Transient Response
When transitioning from Burst Mode operation to fixed frequency, the system exhibits a transient since the modes of operation have changed. For most systems this transient is acceptable, but the application may have stringent input current and/or output voltage requirements that dictate a broad-band voltage loop to minimize the transient. Lowering the DC gain of the loop will facilitate the task (10M FB to Vc) at the expense of DC load regulation.
Figure 5 Soft-Start Circuitry
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Rev. B, Sep 2005
Applications Information (1)
Recommended Component Placement.
Output Capacitor Selection
The bulk value of the capacitor is set to reduce the ripple due to charge into the capacitor each cycle. The steady state ripple due to charge is given by:
ML3440
%Ripple_Boost = %Ripple_Buck =
Iout (max) *( VOUT - VIN (min)) 100
COUT VOUT 2 f Iout (max) *( VIN (max)- VOUT) 100 COUT Vin(max) VOUT * f
% %
where COUT=output filter capacitor, F The output capacitance is usually many times larger in order to handle the transient response of the converter. For a rule of thumb, the ratio of the operating frequency to the unity-gain bandwidth of the converter is the amount of the output capacitance will have to increase from the above calculations in order to maintain the desired transient response. The other component of ripple is due to the ESR (equivalent series resistance) of the output capacitor. Low ESR capacitors should be used to minimize output voltage ripple.
Inductor Selection
The high frequency operation of the ML3440 allows the use of small surface mount inductors. The inductor current ripple is typically set to 20% to 40% of the maximum inductor current. For a given ripple the inductance terms are given as follows: VIN (min)2 * (VOUT - VIN (min)) 100 f Iout (max) %Ripple VOUT 2 VOUT (VIN (max)- VOUT) 100 f Iout (max) %Ripple VIN (max)
L> L>
H H
Input Capacitor Selection
Since the VIN pin is the supply voltage for the IC It is recommended to place at least a 4.7uF, low ESR bypass capacitor.
where f = operating frequency, Hz %Ripple = allowable inductor current ripple,% VIN (Min) = minimum input voltage, V VIN (Max) = maximum input voltage, V VOUT = output voltage, V Iout (Max) = maximum output load current For high efficiency, choose and inductor with a high frequency core material, such as ferrite, to reduce core loses. The inductor should have low ESR (equivalent series resistance) to reduce the I2R losses, and must be able to handle the peak inductor current without saturating. Molded chokes or chip inductors usually do not have enough core to support the peak inductor currents in the 1A to 2A region. To minimize radiated noise, use a toroid, pot core or shielded bobbin inductor.
Optional Schottky Diodes
To achieve a 1%-2% efficiency improvement above 50mW, Schottky diodes can be added across synchronous switches B (SW1 to GND) and D (SW2 to VOUT). The Schottky diodes will provide a lower voltage drop during the break-before-make time (typically 15ns) of the NMOS to PMOS transition. General purpose diodes such as a 1N914 are not recommended due to the slow recovery times and will compromise efficiency. If desired a large Schottky diode, such as an MBRM120T3, can be used from SW2 to VOUT. A small diode, such as ZHCS400 from Zetex or CMDSH2-3 from Central Semiconductor, can be used from SW1 to GND.
Output Voltage>4.3V
A Schottky diode from SW to VOUT is required for output voltages over 4.3V. The diode must be located as close to the pins as possible in order to reduce the peak voltage on SW2 due to the parasitic lead and trace inductance.
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Rev. B, Sep 2005
Applications Information (2)
Input Voltage>4.5V
For applications with input voltages above 4.5V which could exhibit an overload or short-circuit condition, a 2/1nF series snubber is required between the SW1 pin and GND. A Schottky diode from SW1 to VIN should also be added as close to the pins as possible. For the higher input voltages VIN bypassing becomes more critical, therefore, a ceramic bypass capacitor as close to the VIN and GND pins as possible is also required. A troublesome feature in Boost mode is the right-half plane zero(rhp), and is given by: VIN 2
RHPZ
f
=
2 Iout L VOUT
Hz
Operating Frequency Selection
There are several considerations in selecting the operating frequency of the converter. The first is, what are the operating sensitive frequency bands that cannot tolerate any spectral noise? For example, in products incorporating RF Communications, the 455KHz IF frequency is sensitive to any noise, therefore switching above 600 KHz is desired. Some communications have sensitivity to 1.1MHz and in that case a 2MHz converter frequency may be employed. Other considerations are the physical size of the converter and efficiency. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The trade off is in efficiency since the switching losses due to gate charge are going up proportional with frequency. Additional quiescent current due to the output switches GATE charge is given by: Buck : 500e VIN F Boost : 250e-12 (VIN + VOUT) F Buck/Boost : F (750e-12 VIN +250e-12 Vout) where F = switching frequency
-12
The loop gain is typically rolled off before the RHP zero frequency. A simple Type 1 compensation network can be incorporated to stabilize the loop but at cost of reduced bandwidth and slower transient response. To ensure proper phase margin, the loop requires to be crossed over a decade before the LC double pole. The unity-gain frequency of the error amplifier with the Type 1 compensation is given by: 1 2 R1 CP1
fUG =
Hz
Most applications demand an improved transient response to allow a smaller output filter capacitor. To achieve a higher bandwidth, Type 3 compensation is required. Two zeros are required to compensate for the double-pole response. 1 2 32e
3
fPOLE1 =
R1 CP1
Hz
which is extremely close to DC 1 2 RZ CP1 1 2 R1 CZ1 1 2 RZ CP2
fZERO1 = fZERO2 = fZERO3 =
Hz Hz Hz
Closing the Feedback Loop (1)
The ML3440 incorporated voltage mode PWM control. The control to output gain varies with operation region (Buck, Boost, Buck-Boost), but is usually no greater than 15. The output filter exhibits a double pole response is given by: 1 2 L COUT
fFilter_pole =
Hz
Where COUT is the output filter capacitor The output filter zero is given by: 1 2 RESR COUT
fFilter_zero =
Hz
Figure 7. Error Amplifier with Type 1 Compensation
where RESR is the capacitor equivalent series resistance.
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Rev. B, Sep 2005
Applications Information (3)
Restart Circuit
For a sustained short-circuit the circuit in figure 9 will force a soft-start condition. The only design constraint is that R2/C2 time constant must be longer than the soft-start components R1/C1 to ensure start-up.
Figure 8. Error Amplifier with Type 3 Compensation
Short-Circuit Improvements
The ML3440 is current limited to 2.7A peak to protect the IC from damage. At input voltages above 4.5V a current Limit condition may produce undesirable voltages to the IC due to the series inductance of the package, as well as the traces and external components. Following the recommendations for output voltage > 4.3V and input voltage > 4.5V will improve this condition. Addition short -circuit protection can be accomplished with some external circuitry. In an overload or short-circuit condition, the ML3440 voltage loop opens and the error amp control voltage on the Vc pin slams to the upper clamp level. This condition forces boost mode operation in order to attempt to provide more output voltage and the IC hits a peak switch current limit of 2.7A. When switch current limit is reached switches B and D turn on for the remainder of the cycle to reverse the volts seconds on the inductor. Although this prevents current run away, this condition produces four switch operation producing a current foldback characteristic and the average input current drops. The IC is trimmed to guarantee greater than 1A average input current to meet the maximum load demand, but in a short-circuit or overload condition the foldback characteristic will occur producing higher peak switch currents. To minimize this effect during this condition the following circuits can be utilized.
Figure 9 Soft-Start Reset Circuitry for a Sustained Short-Circuit
Simple Average Input Current Control
A simple average current limit circuit is show in figure 10. Once the input current of the IC is above approximately 1A, Q1 will start sourcing current into the FB pin and lower the output voltage to maintain the average input current. Since the voltage loop is utilized to perform average current limit, the voltage control loop is maintained the Vc voltage does not slam. The averaging function of current comes from the fact that voltage loop compensation is also used with this circuit.
Figure 10. Simple Input Current Control Utilizing the Voltage Loop
10/13
Rev. B, Sep 2005
Typical Application Circuits
ML3440
Figure 11
ML3440
Figure 12
ML3440
Figure 13
11/13
Rev. B, Sep 2005
Typical Application Circuits
ML3440
Figure 14
ML3440
Figure 15
12/13
Rev. B, Sep 2005
Package Dimensions
Recommended Solder Pad Layout
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use.
13/13
Rev. B, Sep 2005

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